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may 2000 1 ? 2000 actel corporation v 3 . 0 . 1 54sx family fpgas leading edge performance ? 320 mhz internal performance 3.7 ns clock-to-out (pin-to-pin) 0.1 ns input set-up 0.25 ns clock skew specifications 12,000 to 48,000 system gates up to 249 user-programmable i/o pins up to 1080 flip-flops 0.35 cmos features 66 mhz pci cpld and fpga integration single chip solution 100% resource utilization with 100% pin locking 3.3v operation with 5.0v input tolerance very low power consumption deterministic, user-controllable timing unique in-system diagnostic and debug capability with silicon explorer ii boundary scan testing in compliance with ieee standard 1149.1 (jtag) secure programming technology prevents reverse engineering and design theft sx product profile a54sx08 a54sx16 a54sx16p a54sx32 capacity typical gates system gates 8,000 12,000 16,000 24,000 16,000 24,000 32,000 48,000 logic modules combinatorial cells 768 512 1,452 924 1,452 924 2,880 1800 register cells (dedicated flip-flops) 256 528 528 1,080 maximum user i/os 130 175 175 249 clocks 3333 jtag ye s ye s ye s y e s pci ??yes? clock-to-out 3.7 ns 3.9 ns 4.4 ns 4.6 ns input set-up (external) 0.8 ns 0.5 ns 0.5 ns 0.1 ns speed grades std, ?1, ?2, ?3 std, ?1, ?2, ?3 std, ?1, ?2, ?3 std, ?1, ?2, ?3 temperature grades c, i, m c, i, m c, i, m c, i, m packages (by pin count) plcc pqfp vqfp tqfp pbga fbga 84 208 100 144, 176 ? 144 ? 208 100 176 ? ? ? 208 100 144, 176 ? ? ? 208 ? 144, 176 313, 329 ?
2 general description actel ? s sx family of fpgas features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other fpga architecture. sx devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications. actel ? s sx architecture features two types of logic modules, the combinatorial cell (c-cell) and the register cell (r-cell), each optimized for fast and efficient mapping of synthesized logic functions. the routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. this enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or ? sea-of-modules ? ), which reduces the distance signals have to travel between logic modules. to minimize signal propagation delay, sx devices employ both local and general routing resources. the high-speed local routing resources (directconnect and fastconnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. the general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or i/o module. within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three antifuses). the unique local and general routing structure featured in sx devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent pcb development, reduces design time, and allows designers to achieve performance goals with minimum effort. further complementing sx ? s flexible routing structure is a hard-wired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the i/o cells to achieve fast clock-to-out or fast input set-up times. sx devices have easy-to-use i/o cells that do not require hdl instantiation, facilitating design re-use and reducing design and verification time. ordering information application (temperature range) blank = commercial (0 to +70 c) i = industrial ( ? 40 to +85 c) m = military ( ? 55 to +125 c) pp = pre-production package type bg = ball grid array pl = plastic leaded chip carrier pq = plastic quad flat pack tq = thin (1.4 mm) quad flat pack vq = very thin (1.0 mm) quad flat pack fg = fine pitch ball grid array (1.0 mm) speed grade blank = standard speed ? 1 = approximately 15% faster than standard ? 2 = approximately 25% faster than standard ? 3 = approximately 35% faster than standard part number a54sx08 = 12,000 system gates a54sx16 = 24,000 system gates a54sx16p = 24,000 system gates a54sx32 = 48,000 system gates package lead count a54sx16 ? pq 208 2 blank = not pci compliant p = pci compliant p
3 54sx family fpgas product plan speed grade* application std ? 1 ? 2 ? 3ci ? m a54sx08 device 84-pin plastic leaded chip carrier (plcc) ???? ?? ? 100-pin very thin plastic quad flat pack (vqfp) ???? ?? ? 144-pin thin quad flat pack (tqfp) ???? ?? ? 144-pin fine pitch ball grid array (fbga) ???? ?? ? 176-pin thin quad flat pack (tqfp) ???? ?? ? 208-pin plastic quad flat pack (pqfp) ???? ?? ? a54sx16 device 100-pin very thin plastic quad flat pack (vqfp) ???? ?? p 176-pin thin quad flat pack (tqfp) ???? ?? p 208-pin plastic quad flat pack (pqfp) ???? ?? p a54sx16p device 100-pin very thin plastic quad flat pack (vqfp) ???? ?? ? 144-pin thin quad flat pack (tqfp) ???? ?? ? 176-pin thin quad flat pack (tqfp) ???? ?? ? 208-pin plastic quad flat pack (pqfp) ???? ?? ? a54sx32 device 144-pin thin quad flat pack (tqfp) ???? ?? p 176-pin thin quad flat pack (tqfp) ???? ?? p 208-pin plastic quad flat pack (pqfp) ???? ?? p 313-pin plastic ball grid array (pbga) ???? ?? ? 329-pin plastic ball grid array (pbga) ???? ?? ? contact your actel sales representative for product availability. applications: c = commercial availability: ? = available *speed grade: ?1 = approx. 15% faster than standard i = industrial p = planned ?2 = approx. 25% faster than standard m = military ? = not planned ?3 = approx. 35% faster than standard ? only std, ?1, ?2 speed grade ? only std, ? 1 speed grade plastic device resources user i/os (including clock buffers) device plcc 84-pin vqfp 100-pin pqfp 208-pin tqfp 144-pin tqfp 176-pin pbga 313-pin pbga 329-pin fbga 144-pin a54sx08 69 81 130 113 128 ?? 111 a54sx16 ? 81 175 ? 147 ??? a54sx16p ? 81 175 113 147 ??? a54sx32 ?? 174 113 147 249 249 ? package definitions (consult your local actel sales representative for product availability.) plcc = plastic leaded chip carrier, pqfp = plastic quad flat pack, tqfp = thin quad flat pack, vqfp = very thin quad flat pack, pbga = plastic ball grid array, fbga = fine pitch (1.0 mm) ball grid array
4 sx family architecture the sx family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. programmable interconnect element the sx family provides efficient use of silicon by locating the routing interconnect resources between the metal 2 (m2) and metal 3 (m3) layers ( figure 1 ). this completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on sram fpgas and previous generations of antifuse fpgas), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. interconnection between these logic modules is achieved using actel ? s patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the m2 and m3 layers. the antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. the extremely small size of these interconnect elements gives the sx family abundant routing resources and provides excellent protection against design pirating. reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. logic module design the sx family architecture is described as a ? sea-of-modules ? architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. actel ? s sx family provides two types of logic modules, the register cell (r-cell) and the combinatorial cell (c-cell). the r-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the s0 and s1 lines) control signals ( figure 2 on page 5 ). the r-cell registers feature programmable clock polarity selectable on a register-by-register basis. this provides additional flexibility while allowing mapping of synthesized functions into the sx fpga. the clock source for the r-cell can be chosen from either the hard-wired clock or the routed clock. figure 1 ? sx family interconnect elements silicon substrate tungsten plug contact metal 1 metal 2 metal 3 routing tracks amorphous silicon/ dielectric antifuse tungsten plug via tungsten plug via
5 54sx family fpgas the c-cell implements a range of combinatorial functions up to 5-inputs ( figure 3 ). inclusion of the db input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the sx architecture. an example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-or function into a single c-cell. this facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. at the same time, the c-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. chip architecture the sx family ? s chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. module organization actel has arranged all c-cell and r-cell logic modules into horizontal banks called clusters . there are two types of clusters: type 1 contains two c-cells and one r-cell, while type 2 contains one c-cell and two r-cells. to increase design efficiency and device performance, actel has further organized these modules into superclusters ( figure 4 on page 6 ). supercluster 1 is a two-wide grouping of type 1 clusters. supercluster 2 is a two-wide group containing one type 1 cluster and one type 2 cluster. sx devices feature more supercluster 1 modules than supercluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. figure 2 r-cell figure 3 c-cell direct connect input clka, clkb, internal logic hclk cks ckp clrb psetb y dq routed data input s0 s1 d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y
6 routing resources clusters and superclusters can be connected through the use of two innovative local routing resources called fastconnect and directconnect, which enable extremely fast and predictable interconnection of modules within clusters and superclusters ( figure 5 and figure 6 on page 7 ). this routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. directconnect is a horizontal routing resource that provides connections from a c-cell to its neighboring r-cell in a given supercluster. directconnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. fastconnect enables horizontal routing between any two logic modules within a given supercluster and vertical routing with the supercluster immediately below it. only one programmable connection is used in a fastconnect path, delivering maximum pin-to-pin propagation of 0.4 ns. in addition to directconnect and fastconnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. actel ? s segmented routing structure provides a variety of track lengths for extremely fast routing between superclusters. the exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place and route software to minimize signal propagation delays. actel ? s high-drive routing structure provides three clock networks. the first clock, called hclk, is hard wired from the hclk buffer to the clock select mux in each r-cell. this provides a fast propagation path for the clock signal, enabling the 3.7 ns clock-to-out (pin-to-pin) performance of the sx devices. the hard-wired clock is tuned to provide clock skew as low as 0.25 ns. the remaining two clocks (clka, clkb) are global clocks that can be sourced from external pins or from internal logic signals within the sx device. figure 4 cluster organization type 1 supercluster type 2 supercluster cluster 1 cluster 1 cluster 2 cluster 1 r-cell c-cell d0 d1 d2 d3 db a0 b0 a1 b1 sa sb y direct connect input clka, clkb, internal logic hclk cks ckp clrb psetb y dq routed data input s0 s1
7 54sx family fpgas other architectural features technology actel ? s sx family is implemented on a high-voltage twin-well cmos process using 0.35 design rules. the metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ( ? on ? state) resistance of 25 ? with capacitance of 1.0 ff for low signal impedance. figure 5 directconnect and fastconnect for type 1 superclusters figure 6 directconnect and fastconnect for type 2 superclusters type 1 superclusters routing segments ? typically 2 antifuses max. 5 antifuses fast connect one antifuse 0.4 ns routing delay direct connect no antifuses 0.1 ns routing delay type 2 superclusters routing segments typically 2 antifuses max. 5 antifuses fast connect one antifuse 0.4 ns routing delay direct connect no antifuses 0.1 ns routing delay
8 performance the combination of architectural features described above enables sx devices to operate with internal clock frequencies exceeding 300 mhz, enabling very fast execution of even complex logic functions. thus, the sx family is an optimal platform upon which to integrate the functionality previously contained in multiple cplds. in addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an sx device with dramatic improvements in cost and time to market. using timing-driven place and route tools, designers can achieve highly deterministic device performance. with sx devices, designers do not need to use complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macros in hdl code to achieve high performance. i/o modules each i/o on an sx device can be configured as an input, an output, a tristate output, or a bidirectional pin. even without the inclusion of dedicated i/o registers, these i/os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns. i/o cells that have embedded latches and flip-flops require instantiation in hdl code; this is a design complication not encountered in sx fpgas. fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. power requirements the sx family supports 3.3v operation and is designed to tolerate 5.0v inputs. ( table 1 ). power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. power requirements are further reduced because of the small number of low-resistance antifuses in the path. the antifuse architecture does not require active circuitry to hold a charge (as do sram or eprom), making it the lowest-power architecture on the market. boundary scan testing (bst) all sx devices are ieee 1149.1 compliant. sx devices offer superior diagnostic and testing capabilities by providing boundary scan testing (bst) and probing capabilities. these functions are controlled through the special test pins in conjunction with the program fuse. the functionality of each pin is described in table 2 .in the dedicated test mode, tck, tdi and tdo are dedicated pins and cannot be used as regular i/os. in flexible mode, tms should be set high through a pull-up resistor of 10k ? . tms can be pulled low to initiate the test sequence. the program fuse determines whether the device is in dedicated or flexible mode. the default (fuse not blown) is flexible mode. . development tool support the sx devices are fully supported by actel ? s line of fpga development tools, including the actel desktop series and designer advantage tools. the actel desktop series is an integrated design environment for pcs that includes design entry, simulation, synthesis, and place and route tools. designer advantage, actel ? s suite of fpga development point tools for pcs and workstations, includes the actgen macro builder, designer with directtime timing driven place and route and analysis tools, and device programming software. in addition, the sx devices contain actionprobe circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. the probe circuitry is accessed by silicon explorer ii, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 mhz (asynchronous) or 66 mhz (synchronous). silicon explorer ii attaches to a pc ? s standard com port, turning the pc into a fully functional 18-channel logic analyzer. silicon explorer ii allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. sx probe circuit control pins the silicon explorer ii tool uses the boundary scan ports (tdi, tck, tms and tdo) to select the desired nets for verification. the selected internal nets are assigned to the pra/prb pins for observation. figure 7 illustrates the table 1 supply voltages v cca v cci v ccr input to ler an ce output drive a54sx08 a54sx16 a54sx32 3.3v 3.3v 5.0v 3.3v 3.3v 3.3v 3.3v 5.0v 5.0v 3.3v a54sx16p 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 5.0v 5.0v 3.3v 3.3v 5.0v 5.0v 5.0v 5.0v table 2 boundary scan pin functionality program fuse blown (dedicated test mode) program fuse not blown (flexible mode) tck, tdi, tdo are dedi- cated bst pins tck, tdi, tdo are flexible and may be used as i/os no need for pull-up resistor for tms use a pull-up resistor of 10k ? on tms
9 54sx family fpgas interconnection between silicon explorer ii and the fpga to perform in-circuit verification. the trst pin is equipped with a pull-up resistor. to remove the boundary scan state machine from the reset state during probing, it is recommended that the trst pin be left floating. design considerations the tdi, tck, tdo, pra, and prb pins should not be used as input or bidirectional ports. because these pins are active during probing, critical signals input through these pins are not available while probing. in addition, the security fuse should not be programmed because doing so disables the probe circuitry. figure 7 probe setup sx fpga silicon explorer ii tdi tck tdo tms pra prb serial connection 18 channels
10 3.3v/5v operating conditions absolute maximum ratings 1 symbol parameter limits units v ccr 2 dc supply voltage 3 ? 0.3 to +6.0 v v cca 2 dc supply voltage ? 0.3 to +4.0 v v cci 2 dc supply voltage (a54sx08, a54sx16, a54sx32) ? 0.3 to +4.0 v v cci 2 dc supply voltage (a54sx16p) ? 0.3 to +6.0 v v i input voltage ? 0.5 to +5.5 v v o output voltage ? 0.5 to +3.6 v i io i/o source sink current 3 ? 30 to +5.0 ma t stg storage temperature ? 40 to +125 c notes: 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. v ccr in the a54sx16p must be greater than or equal to v cci during power-up and power-down sequences and during normal operation. 3. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5v or less than gnd ? 0.5v, the internal protection diodes will forward-bias and can draw excessive current. recommended operating conditions parameter commercial industrial military units temperature range 1 0 to+70 ? 40 to +85 ? 55 to +125 c 3.3v power supply tolerance 10 10 10 %v cc 5.0v power supply tolerance 5 10 10 %v cc note: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military. electrical specifications commercial industrial symbol parameter min. max. min. max. units v oh (i oh = -20ua) (cmos) (i oh = -8ma) (ttl) (i oh = -6ma) (ttl) (v cci ? 0.1) 2.4 v cci v cci (v cci ? 0.1) 2.4 v cci v cci v v ol (i ol = 20ua) (cmos) (i ol = 12ma) (ttl) (i ol = 8ma) (ttl) 0.10 0.50 0.50 v v il 0.8 0.8 v v ih 2.0 2.0 v t r , t f input transition time t r , t f 50 50 ns c io c io i/o capacitance 10 10 pf i cc standby current, i cc 4.0 4.0 ma i cc(d) i cc(d) i dynamic v cc supply current see ? evaluating power in 54sx devices ? on page 18.
11 54sx family fpgas pci compliance for the 54sx family the 54sx family supports 3.3v and 5v pci and is compliant with the pci local bus specification rev. 2.1. a54sx16p dc specifications (5.0v pci operation) symbol parameter condition min. max. units v cca supply voltage for array 3.0 3.6 v v ccr supply voltage required for internal biasing 4.75 5.25 v v cci supply voltage for ios 4.75 5.25 v v ih input high voltage 1 2.0 v cc + 0.5 v v il input low voltage 1 ? 0.5 0.8 v i ih input high leakage current v in = 2.7 70 a i il input low leakage current v in = 0.5 ? 70 a v oh output high voltage i out = ? 2 ma 2.4 v v ol output low voltage 2 i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 4 8pf notes: 1. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 2. signals without pull-up resistors must have 3 ma low output current. signals requiring pull up must have 6 ma; the latter inc lude, frame#, irdy#, trdy#, devsel#, stop#, serr#, perr#, lock#, and, when used ad[63::32], c/be[7::4]#, par64, req64#, and ack64#. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk). 4. lower capacitance on this input-only pin allows for non-resistive coupling to ad[xx].
12 a54sx16p ac specifications for (pci operation) symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 1.4 1 ? 44 ma 1.4 v out < 2.4 1, 2 ? 44 + (v out ? 1.4)/0.024 ma 3.1 < v out < v cc 1, 3 equation a: on page 13 (test point) v out = 3.1 3 ? 142 ma i ol(ac) switching current high v out 2.2 1 95 ma 2.2 > v out > 0.55 1 v out /0.023 0.71 > v out > 0 1, 3 equation b: on page 13 ma (test point) v out = 0.71 3 206 ma i cl low clamp current ? 5 < v in ? 1 ? 25 + (v in + 1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 4 15v/ns slew f output fall slew rate 2.4v to 0.4v load 4 15v/ns notes: 1. refer to the v/i curves in figure 8 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst# which are system outputs. ? switching current high ? specification are not relevant to serr#, inta#, intb#, intc#, and intd# which are open drain outputs. 2. note that this segment of the minimum current curve is drawn from the ac drive point directly to the dc drive point rather th an toward the voltage rail (as is done in the pull-down curve). this difference is intended to allow for an optional n-channel pull-up. 3. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (a a nd b) are provided with the respective diagrams in figure 8 . the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rat e at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this paramete r with an unloaded output per revision 2.0 of the pci local bus specification. however, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity modeling accounts for this. rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. v cc 1k ? 10 pf 1k ? pin
13 54sx family fpgas figure 8 shows the 5.0v pci v/i curve and the minimum and maximum pci drive characteristics of the a54sx16p family. equation a: i oh = 11.9 * (v out ? 5.25) * (v out + 2.45) for v cc > v out > 3.1v equation b: i ol = 78.5 * v out * (4.4 ? v out ) for 0v < v out < 0.71v figure 8 5.0v pci curve for a54sx16p family 1 23456 ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 voltage out current (a) sx pci i ol sx pci i oh pci i ol maximum pci i oh maximum pci i oh minimum pci i ol minimum
14 a54sx16p dc specifications (3.3v pci operation) symbol parameter condition min. max. units v cca supply voltage for array 3.0 3.6 v v ccr supply voltage required for internal biasing 3.0 3.6 v v cci supply voltage for ios 3.0 3.6 v v ih input high voltage 0.5v cc v cc + 0.5 v v il input low voltage ? 0.5 0.3v cc v i ipu input pull-up voltage 1 0.7v cc v i il input leakage current 2 0 < v in < v cc 10 a v oh output high voltage i out = ? 500 a 0.9v cc v v ol output low voltage i out = 1500 a 0.1v cc v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 4 8pf notes: 1. this specification should be guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pul l a floated network. applications sensitive to static power utilization should assure that the input buffer is conducting minimum current a t this input voltage. 2. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 3. absolute maximum pin capacitance for a pci input is 10pf (except for clk). 4. lower capacitance on this input-only pin allows for non-resistive coupling to ad[xx].
15 54sx family fpgas a 54sx16p ac specifications (3.3v pci operation) symbol parameter condition min. max. units switching current high 0 < v out 0.3v cc 1 ma 0.3v cc v out < 0.9v cc 1 ? 12v cc ma i oh(ac) 0.7v cc < v out < v cc 1, 2 ? 17.1 + (v cc ? v out ) equation c: on page 16 (test point) v out = 0.7v cc 2 ? 32v cc ma switching current high v cc > v out 0.6v cc 1 ma 0.6v cc > v out > 0.1v cc 1 16v cc ma i ol(ac) 0.18v cc > v out > 0 1, 2 26.7v out on page 16 ma (test point) v out = 0.18v cc 2 38v cc i cl low clamp current ? 3 < v in ? 1 ? 25 + (v in + 1)/0.015 ma i ch high clamp current ? 3 < v in ? 1 25 + (v in ? v out ? 1)/0.015 ma slew r output rise slew rate 3 0.2v cc to 0.6v cc load 1 4 v/ns slew f output fall slew rate 3 0.6v cc to 0.2v cc load 1 4 v/ns notes: 1. refer to the v/i curves in figure 9 . switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst# which are system outputs. ? switching current high ? specification are not relevant to serr#, inta#, intb#, intc#, and intd# which are open drain outputs. 2. maximum current requirements must be met as drivers pull beyond the last step voltage. equations defining these maximums (c a nd d) are provided with the respective diagrams in figure 9 . the equation defined maxima should be met by design. in order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. this parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rat e at any point within the transition range. the specified load (diagram below) is optional; i.e., the designer may elect to meet this paramete r with an unloaded output per the latest revision of the pci local bus specification. however, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). rise slew rate does not apply to open drain outputs. output buffer 1/2 in. max. v cc 1k ? 10 pf 1k ? pin
16 figure 9 shows the 3.3v pci v/i curve and the minimum and maximum pci drive characteristics of the a54sx16p family. equation c: i oh = (98.0/v cc ) * (v out ? v cc ) * (v out + 0.4v cc ) for v cc > v out > 0.7 v cc equation d: i ol = (256/v cc ) * v out * (v cc ? v out ) for 0v < v out < 0.18 v cc figure 9 3.3v pci curve for a54sx16p family 123456 voltage out ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current (a) sx pci i ol sx pci i oh pci i ol maximum pci i oh maximum pci i oh minimum pci i ol minimum
17 54sx family fpgas power-up sequencing power-down sequencing v cca v ccr v cci power-up sequence comments a54sx08, a54sx16, a54sx32 3.3v 5.0v 3.3v 5.0v first 3.3v second no possible damage to device. 3.3v first 5.0v second possible damage to device. a54sx16p 3.3v 3.3v 3.3v 3.3v only no possible damage to device. 3.3v 5.0v 3.3v 5.0v first 3.3v second no possible damage to device. 3.3v first 5.0v second possible damage to device. 3.3v 5.0v 5.0v 5.0v first 3.3v second no possible damage to device. 3.3v first 5.0v second no possible damage to device. v cca v ccr v cci power-down sequence comments a54sx08, a54sx16, a54sx32 3.3v 5.0v 3.3v 5.0v first 3.3v s econd p o s s i b l e d a m a ge t o d e v i c e . 3.3v first 5.0v s econd no p o ss i b l e da m age to d e v i c e . a54sx16p 3.3v 3.3v 3.3v 3.3v only no possible damage to device. 3.3v 5.0v 3.3v 5.0v first 3.3v second possible damage to device. 3.3v first 5.0v second no possible damage to device. 3.3v 5.0v 5.0v 5.0v first 3.3v second no possible damage to device. 3.3v first 5.0v second no possible damage to device.
18 evaluating power in 54sx devices a critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. the thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system ? s ability to dissipate heat. you should complete a power evaluation early in the design process to help identify potential heat-related problems in the system and to prevent the system from exceeding the device ? s maximum allowed junction temperature. the actual power dissipated by most applications is significantly lower than the power the package can dissipate. however, a thermal analysis should be performed for all projects. to perform a power evaluation, follow these steps: estimate the power consumption of the application. calculate the maximum power allowed for the device and package. compare the estimated power and maximum power values. estimating power consumption the total power dissipation for the 54sx family is the sum of the dc power dissipation and the ac power dissipation. use equation 1 to calculate the estimated power consumption of your application. p total = p dc + p ac (1) dc power dissipation the power due to standby current is typically a small component of the overall power. the standby power is shown below for commercial, worst case conditions (70 c). the dc power dissipation is defined in equation 2 as follows: p dc = (i standby )*v cca + (i standby )*v ccr + (i standby )*v cci + x*v ol *i ol + y*(v cci ? v oh )*v oh (2) ac power dissipation the power dissipation of the 54sx family is usually dominated by the dynamic power dissipation. dynamic power dissipation is a function of frequency, equivalent capacitance and power supply voltage. the ac power dissipation is defined as follows: p ac = p module + p rclka net + p rclkb net + p hclk net + p output buffer + p input buffer (3) p ac = v cca 2 * [(m * c eqm * f m ) module + (n * c eqi * f n ) input buffer + (p * (c eqo + c l ) * f p ) output buffer + (0.5 * (q 1 * c eqcr * f q1 ) + (r 1 * f q1 )) rclka + (0.5 * (q 2 * c eqcr * f q2 )+ (r 2 * f q2 )) rclkb + (0.5 * (s 1 * c eqhv * f s1 ) + (c eqhf * f s1 )) hclk ](4) definition of terms used in formula table 3 i cc v cc power 4ma 3.6v 14.4mw m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock x = number of i/os at logic low y = number of i/os at logic high r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock s 1 = number of clock loads on the dedicated array clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c eqhv = variable capacitance of dedicated array clock c eqhf = fixed capacitance of dedicated array clock c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz f s1 = average dedicated array clock rate in mhz a54sx08 a54sx16 a54sx16p a54sx32 c eqm (pf) 4.0 4.0 4.0 4.0 c eqi (pf) 3.4 3.4 3.4 3.4 c eqo (pf) 4.7 4.7 4.7 4.7 c eqcr (pf) 1.6 1.6 1.6 1.6 c eqhv 0.615 0.615 0.615 0.615 c eqhf 60 96 96 140 r 1 (pf) 87 138 138 171 r 2 (pf) 87 138 138 171
19 54sx family fpgas guidelines for calculating power consumption the following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. these guidelines are as follow: sample power calculation one of the designs used to characterize the a54sx family was a 528 bit serial in serial out shift register. the design utilized 100% of the dedicated flip-flops of an a54sx16p device. a pattern of 0101 ? was clocked into the device at frequencies ranging from 1 mhz to 200 mhz. shifting in a series of 0101 ? caused 50% of the flip-flops to toggle from low to high at every clock cycle. follow the steps below to estimate power consumption. the values provided for the sample calculation below are for the shift register design above. this method for estimating power consumption is conservative and the actual power consumption of your design may be less than the estimated power consumption. the total power dissipation for the 54sx family is the sum of the ac power dissipation and the dc power dissipation. p total = p ac (dynamic power) + p dc (static power) (5) ac power dissipation p ac = p module + p rclka net + p rclkb net + p hclk net + p output buffer + p input buffer (6) p ac = v cca 2 * [(m * c eqm * f m ) module + (n * c eqi * f n ) input buffer + (p * (c eqo + c l ) * f p ) output buffer + (0.5 * (q 1 * c eqcr * f q1 ) + (r 1 * f q1 )) rclka + (0.5 * (q 2 * c eqcr * f q2 )+ (r 2 * f q2 )) rclkb + (0.5 * (s 1 * c eqhv * f s1 ) + (c eqhf * f s1 )) hclk ](7) step #1: define terms used in formula logic modules (m) = 20% of modules inputs switching (n) = # inputs/4 outputs switching (p) = # output/4 first routed array clock loads (q 1 ) = 20% of register cells second routed array clock loads (q 2 ) = 20% of register cells load capacitance (c l )=35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n )=f/5 average output switching rate (f p )=f/10 average first routed array clock rate (f q1 ) =f/2 average second routed array clock rate (f q2 ) =f/2 average dedicated array clock rate (f s1 ) =f dedicated clock array clock loads (s 1 ) = 20% of regular modules v cca 3.3 module number of logic modules switching at f m (used 50%) m264 average logic modules switching rate f m (mhz) (guidelines: f/10) f m 20 module capacitance c eqm (pf) c eqm 4.0 input buffer number of input buffers switching at f n n1 average input switching rate f n (mhz) (guidelines: f/5) f n 40 input buffer capacitance c eqi (pf) c eqi 3.4 output buffer number of output buffers switching at f p p1 average output buffers switching rate f p (mhz) (guidelines: f/10) f p 20 output buffers buffer capacitance c eqo (pf) c eqo 4.7 output load capacitance c l (pf) c l 35 rclka number of clock loads q 1 q 1 528 capacitance of routed array clock (pf) c eqcr 1.6 average clock rate (mhz) f q1 200 fixed capacitance (pf) r 1 138 rclkb number of clock loads q 2 q 2 0 capacitance of routed array clock (pf) c eqcr 1.6 average clock rate (mhz) f q2 0 fixed capacitance (pf) r 2 138 hclk number of clock loads s 1 0 variable capacitance of dedicated array clock (pf) c eqhv 0.615 fixed capacitance of dedicated array clock (pf) c eqhf 96 average clock rate (mhz) f s1 0
20 step #2: calculate dynamic power consumption step #3: calculate dc power dissipation dc power dissipation p dc = (i standby )*v cca + (i standby )*v ccr + (i standby )*v cci + x*v ol *i ol + y*(v cci ? v oh )*v oh (8) for a rough estimate of dc power dissipation, only use p dc =(i standby )*v cca . the rest of the formula provides a very small number that can be considered negligible. p dc = (i standby )*v cca p dc = .55ma*3.3v p dc = 0.001815w step #4: calculate total power consumption p total = p ac + p dc p total = 1.461 + 0.001815 p total = 1.4628w step #5: compare estimated power consumption against characterized power consumption the estimated total power consumption for this design is 1.46w. the characterized power consumption for this design at 200 mhz is 1.0164w. figure 10 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 mhz to 200 mhz. v cca *v cca 10.89 m*f m *c eqm 0.02112 n*f n *c eqi 0.000136 p*f p *(c eqo +c l ) 0.000794 0.5*(q 1 *c eqcr *f q1 )+(r 1 *f q1 ) 0.11208 0.5*(q 2 *c eqcr *f q2 )+(r 2 *f q2 )0 0.5 *(s 1 * c eqhv * f s1 )+(c eqhf *f s1 )0 p ac = 1.461w figure 10 power dissipation 0 200 400 600 800 1000 1200 frequency mhz power dissipation mw 20 0 40 60 80 100 120 140 160 180 200
21 54sx family fpgas junction temperature (t j ) the temperature that you select in designer series software is the junction temperature, not ambient temperature. this is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. use the equation below to calculate junction temperature. junction temperature = ? t + t a where: t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ja * p p = power calculated from estimating power consumption section ja = junction to ambient of package. ja numbers are located in package thermal characteristics section. package thermal characteristics the device junction to case thermal characteristic is jc , and the junction to ambient air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. the maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a tqfp 176-pin package at commercial temperature and still air is as follows: package type pin count jc ja still air ja 300 ft/min units plastic leaded chip carrier (plcc) 84 12 32 22 c/w thin quad flat pack (tqfp) 144 11 32 24 c/w thin quad flat pack (tqfp) 176 11 28 21 c/w very thin quad flatpack (vqfp) 100 10 38 32 c/w plastic quad flat pack (pqfp) without heat spreader 208 8 30 23 c/w plastic quad flat pack (pqfp) with heat spreader 208 3.8 20 17 c/w plastic ball grid array (pbga) 272 3 20 14.5 c/w plastic ball grid array (pbga) 313 3 23 17 c/w plastic ball grid array (pbga) 329 3 18 13.5 c/w fine pitch ball grid array (fbga) 144 3.8 38.8 26.7 c/w note: sx08 does not have a heat spreader. maximum power allowed max. junction temp. (c) ? max. ambient temp. (c) ja (c/w) ------------------------------------------------------------------------------------------------------------------------------ 150c ? 70c 28c/w --------------------------------- 2 . 8 6 w ===
22 54sx timing model* hard-wired clock external set-up = t iny + t ird1 + t sud ? t hckh = 1.5 + 0.3 + 0.5 ? 1.0 = 1.3 ns clock-to-out (pin-to-pin) =t hckh + t rco + t rd1 + t dhl = 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns routed clock external set-up = t iny + t ird1 + t sud ? t rckh = 1.5 + 0.3 + 0.5 ? 1.5 = 0.8 ns clock-to-out (pin-to-pin) =t rckh + t rco + t rd1 + t dhl = 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns *values shown for a54sx08-3, worst-case commercial conditions. output delays internal delays input delays hard-wired i/o module f hmax = 320 mhz t iny = 1.5 ns t ird2 = 0.6 ns combinatorial cell t pd =0.6 ns register cell i/o module t rd1 = 0.3 ns t dhl = 1.6 ns i/o module routed clock f max = 250 mhz d q d q t dhl = 1.6 ns t enzh = 2.3 ns t rd1 = 0.3 ns t rco = 0.8 ns t sud = 0.5 ns t hd = 0.0 ns t rd4 = 1.0 ns t rd8 = 1.9 ns predicted routing delays t rckh = 1.5 ns (100% load) t rd1 = 0.3 ns register cell t rco = 0.8 ns clock t hckh = 1.0 ns
23 54sx family fpgas output buffer delays ac test loads input buffer delays c-cell delays to ac test loads (shown below) pa d d e tribuff in v cc gnd 50% out v ol v oh 1.5v t dlh 50% 1.5v t dhl en v cc gnd 50% out v ol 1.5v t enzl 50% 10% t enlz en v cc gnd 50% out gnd v oh 1.5v t enzh 50% 90% t enhz v cc load 1 (used to measure load 2 (used to measure enable delays) 35 pf to the output v cc gnd 35 pf to the output r to v cc for t pzl r to gnd for t pzh r = 1 k ? propagation delay) under test under test load 3 (used to measure disable delays) v cc gnd 5 pf to the output r to v cc for t plz r to gnd for t phz r = 1 k ? under test pa d y inbuf in 3v 0v 1.5v out gnd v cc 50% t iny 1.5v 50% t iny s a b y s, a or b out gnd v cc 50% t pd out gnd gnd v cc 50% 50% 50% v cc 50% 50% t pd t pd t pd
24 timing characteristics timing characteristics for 54sx devices fall into three categories: family-dependent, device-dependent, and design-dependent. the input and output buffer characteristics are common to all 54sx family members. internal routing delays are device dependent. design dependency means actual delays are not determined until after placement and routing of the user ? s design is complete. delay values may then be determined by using the directtime analyzer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most time-critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. long tracks some nets in the design use long tracks. long tracks are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes five antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 4 ns to 8.4 ns delay. this additional delay is represented statistically in higher fanout (fo=24) routing delays in the data sheet specifications section. timing derating 54sx devices are manufactured in a cmos process. therefore, device performance varies according to temperature, voltage, and process variations. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. temperature and voltage derating factors (normalized to worst-case commercial, t j = 70 c, v cca = 3.0v) register cell timing characteristics flip-flops (positive edge triggered) d clk clr q d clk q clr t hpwh , t was yn t hd t sud t hp t hpwl , t rco t clr t rpwl t rpwh preset t preset preset v cca junction temperature (t j ) ? 55 ? 40 0 25 70 85 125 3.0 0.75 0.78 0.87 0.89 1.00 1.04 1.16 3.3 0.70 0.73 0.82 0.83 0.93 0.97 1.08 3.6 0.66 0.69 0.77 0.78 0.87 0.92 1.02
25 54sx family fpgas a54sx08 timing characteristics (worst-case commercial conditions, v ccr = 4.75v, v cca, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.6 0.7 0.8 0.9 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.4 0.4 0.5 ns t rd1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t rd2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t rd3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t rd4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t rd8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t rd12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns r-cell timing t rco sequential clock-to-q 0.8 1.1 1.2 1.4 ns t clr asynchronous clear-to-q 0.5 0.6 0.7 0.8 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.0 ns t sud flip-flop data input set-up 0.5 0.5 0.7 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.4 1.6 1.8 2.1 ns input module propagation delays t inyh input data pad-to-y high 1.5 1.7 1.9 2.2 ns t inyl input data pad-to-y low 1.5 1.7 1.9 2.2 ns input module predicted routing delays 2 t ird1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t ird2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t ird3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t ird4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t ird8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t ird12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment.
26 a54sx08 timing characteristics (continued) (worst-case commercial conditions) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units dedicated (hard-wired) array clock network t hckh input low to high (pad to r-cell input) 1.0 1.1 1.3 1.5 ns t hckl input high to low (pad to r-cell input) 1.0 1.2 1.4 1.6 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.1 0.2 0.2 0.2 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.3 1.5 1.7 2.0 ns t rckl input high to low (light load) (pad to r-cell input) 1.4 1.6 1.8 2.1 ns t rckh input low to high (50% load) (pad to r-cell input) 1.4 1.7 1.9 2.2 ns t rckl input high to low (50% load) (pad to r-cell input) 1.5 1.7 2.0 2.3 ns t rckh input low to high (100% load) (pad to r-cell input) 1.5 1.7 1.9 2.2 ns t rckl input high to low (100% load) (pad to r-cell input) 1.5 1.8 2.0 2.3 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.1 0.2 0.2 0.2 ns t rcksw maximum skew (50% load) 0.3 0.3 0.4 0.4 ns t rcksw maximum skew (100% load) 0.3 0.3 0.4 0.4 ns ttl output module timing 1 t dlh data-to-pad low to high 1.6 1.9 2.1 2.5 ns t dhl data-to-pad high to low 1.6 1.9 2.1 2.5 ns t enzl enable-to-pad, z to l 2.1 2.4 2.8 3.2 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 ns t enlz enable-to-pad, l to z 1.4 1.7 1.9 2.2 ns t enhz enable-to-pad, h to z 1.3 1.5 1.7 2.0 ns note: 1. delays based on 35 pf loading, except t enzl and t enzh . for t enzl and t enzh the loading is 5 pf.
27 54sx family fpgas a54sx16 timing characteristics (worst-case commercial conditions, v ccr = 4.75v, v cca, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.6 0.7 0.8 0.9 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.4 0.4 0.5 ns t rd1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t rd2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t rd3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t rd4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t rd8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t rd12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns r-cell timing t rco sequential clock-to-q 0.8 1.1 1.2 1.4 ns t clr asynchronous clear-to-q 0.5 0.6 0.7 0.8 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.0 ns t sud flip-flop data input set-up 0.5 0.5 0.7 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.4 1.6 1.8 2.1 ns input module propagation delays t inyh input data pad-to-y high 1.5 1.7 1.9 2.2 ns t inyl input data pad-to-y low 1.5 1.7 1.9 2.2 ns predicted input routing delays 2 t ird1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t ird2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t ird3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t ird4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t ird8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t ird12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment.
28 a54sx16 timing characteristics (continued) (worst-case commercial conditions) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units dedicated (hard-wired) array clock network t hckh input low to high (pad to r-cell input) 1.2 1.4 1.5 1.8 ns t hckl input high to low (pad to r-cell input) 1.2 1.4 1.6 1.9 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.2 0.2 0.3 0.3 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.6 1.8 2.1 2.5 ns t rckl input high to low (light load) (pad to r-cell input) 1.8 2.0 2.3 2.7 ns t rckh input low to high (50% load) (pad to r-cell input) 1.8 2.1 2.5 2.8 ns t rckl input high to low (50% load) (pad to r-cell input) 2.0 2.2 2.5 3.0 ns t rckh input low to high (100% load) (pad to r-cell input) 1.8 2.1 2.4 2.8 ns t rckl input high to low (100% load) (pad to r-cell input) 2.0 2.2 2.5 3.0 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.5 0.5 0.5 0.7 ns t rcksw maximum skew (50% load) 0.5 0.6 0.7 0.8 ns t rcksw maximum skew (100% load) 0.5 0.6 0.7 0.8 ns ttl output moduletiming 1 t dlh data-to-pad low to high 1.6 1.9 2.1 2.5 ns t dhl data-to-pad high to low 1.6 1.9 2.1 2.5 ns t enzl enable-to-pad, z to l 2.1 2.4 2.8 3.2 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 ns t enlz enable-to-pad, l to z 1.4 1.7 1.9 2.2 ns t enhz enable-to-pad, h to z 1.3 1.5 1.7 2.0 ns note: 1. delays based on 35 pf loading, except t enzl and t enzh . for t enzl and t enzh the loading is 5 pf.
29 54sx family fpgas a54sx16p timing characteristics (worst-case commercial conditions, v ccr = 4.75v, v cca, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.6 0.7 0.8 0.9 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.4 0.4 0.5 ns t rd1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t rd2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t rd3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t rd4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t rd8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t rd12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns r-cell timing t rco sequential clock-to-q 0.9 1.1 1.3 1.4 ns t clr asynchronous clear-to-q 0.5 0.6 0.7 0.8 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.0 ns t sud flip-flop data input set-up 0.5 0.5 0.7 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.4 1.6 1.8 2.1 ns input module propagation delays t inyh input data pad-to-y high 1.5 1.7 1.9 2.2 ns t inyl input data pad-to-y low 1.5 1.7 1.9 2.2 ns predicted input routing delays 2 t ird1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t ird2 fo=2 routing delay 0.6 0.7 0.8 0.9 ns t ird3 fo=3 routing delay 0.8 0.9 1.0 1.2 ns t ird4 fo=4 routing delay 1.0 1.2 1.4 1.6 ns t ird8 fo=8 routing delay 1.9 2.2 2.5 2.9 ns t ird12 fo=12 routing delay 2.8 3.2 3.7 4.3 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment.
30 a54sx16p timing characteristics (continued) (worst-case commercial conditions, v ccr = 4.75v, v cca, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units dedicated (hard-wired) array clock network t hckh input low to high (pad to r-cell input) 1.2 1.4 1.5 1.8 ns t hckl input high to low (pad to r-cell input) 1.2 1.4 1.6 1.9 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.2 0.2 0.3 0.3 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 1.6 1.8 2.1 2.5 ns t rckl input high to low (light load) (pad to r-cell input) 1.8 2.0 2.3 2.7 ns t rckh input low to high (50% load) (pad to r-cell input) 1.8 2.1 2.5 2.8 ns t rckl input high to low (50% load) (pad to r-cell input) 2.0 2.2 2.5 3.0 ns t rckh input low to high (100% load) (pad to r-cell input) 1.8 2.1 2.4 2.8 ns t rckl input high to low (100% load) (pad to r-cell input) 2.0 2.2 2.5 3.0 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.5 0.5 0.5 0.7 ns t rcksw maximum skew (50% load) 0.5 0.6 0.7 0.8 ns t rcksw maximum skew (100% load) 0.5 0.6 0.7 0.8 ns ttl output module timing t dlh data-to-pad low to high 2.4 2.8 3.1 3.7 ns t dhl data-to-pad high to low 2.3 2.9 3.2 3.8 ns t enzl enable-to-pad, z to l 3.0 3.4 3.9 4.6 ns t enzh enable-to-pad, z to h 3.3 3.8 4.3 5.0 ns t enlz enable-to-pad, l to z 2.3 2.7 3.0 3.5 ns t enhz enable-to-pad, h to z 2.8 3.2 3.7 4.3 ns ttl/pci output module timing t dlh data-to-pad low to high 1.5 1.7 2.0 2.3 ns t dhl data-to-pad high to low 1.9 2.2 2.4 2.9 ns t enzl enable-to-pad, z to l 2.3 2.6 3.0 3.5 ns t enzh enable-to-pad, z to h 1.5 1.7 1.9 2.3 ns t enlz enable-to-pad, l to z 2.7 3.1 3.5 4.1 ns t enhz enable-to-pad, h to z 2.9 3.3 3.7 4.4 ns
31 54sx family fpgas a54sx16p timing characteristics (continued) (worst-case commercial conditions v ccr = 3.0v, v cca , v cci = 3.0v, t j = 70c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units pci output module timing 1 t dlh data-to-pad low to high 1.8 2.0 2.3 2.7 ns t dhl data-to-pad high to low 1.7 2.0 2.2 2.6 ns t enzl enable-to-pad, z to l 0.8 1.0 1.1 1.3 ns t enzh enable-to-pad, z to h 1.2 1.2 1.5 1.8 ns t enlz enable-to-pad, l to z 1.0 1.1 1.3 1.5 ns t enhz enable-to-pad, h to z 1.1 1.3 1.5 1.7 ns ttl output module timing t dlh data-to-pad low to high 2.1 2.5 2.8 3.3 ns t dhl data-to-pad high to low 2.0 2.3 2.6 3.1 ns t enzl enable-to-pad, z to l 2.5 2.9 3.2 3.8 ns t enzh enable-to-pad, z to h 3.0 3.5 3.9 4.6 ns t enlz enable-to-pad, l to z 2.3 2.7 3.1 3.6 ns t enhz enable-to-pad, h to z 2.9 3.3 3.7 4.4 ns note: 1. delays based on 10 pf loading.
32 a54sx32 timing characteristics (worst-case commercial conditions, v ccr = 4.75v, v cca, v cci = 3.0v, t j = 70 c) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units c-cell propagation delays 1 t pd internal array module 0.6 0.7 0.8 0.9 ns predicted routing delays 2 t dc fo=1 routing delay, direct connect 0.1 0.1 0.1 0.1 ns t fc fo=1 routing delay, fast connect 0.3 0.4 0.4 0.5 ns t rd1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t rd2 fo=2 routing delay 0.7 0.8 0.9 1.0 ns t rd3 fo=3 routing delay 1.0 1.2 1.4 1.6 ns t rd4 fo=4 routing delay 1.4 1.6 1.8 2.1 ns t rd8 fo=8 routing delay 2.7 3.1 3.5 4.1 ns t rd12 fo=12 routing delay 4.0 4.7 5.3 6.2 ns r-cell timing t rco sequential clock-to-q 0.8 1.1 1.3 1.4 ns t clr asynchronous clear-to-q 0.5 0.6 0.7 0.8 ns t preset asynchronous preset-to-q 0.7 0.8 0.9 1.0 ns t sud flip-flop data input set-up 0.5 0.6 0.7 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 1.4 1.6 1.8 2.1 ns input module propagation delays t inyh input data pad-to-y high 1.5 1.7 1.9 2.2 ns t inyl input data pad-to-y low 1.5 1.7 1.9 2.2 ns predicted input routing delays 2 t ird1 fo=1 routing delay 0.3 0.4 0.4 0.5 ns t ird2 fo=2 routing delay 0.7 0.8 0.9 1.0 ns t ird3 fo=3 routing delay 1.0 1.2 1.4 1.6 ns t ird4 fo=4 routing delay 1.4 1.6 1.8 2.1 ns t ird8 fo=8 routing delay 2.7 3.1 3.5 4.1 ns t ird12 fo=12 routing delay 4.0 4.7 5.3 6.2 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t rco + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment.
33 54sx family fpgas a54sx32 timing characteristics (continued) (worst-case commercial conditions) ?? 3 ? speed ?? 2 ? speed ?? 1 ? speed ? std ? speed parameter description min. max. min. max. min. max. min. max. units dedicated (hard-wired) array clock network t hckh input low to high (pad to r-cell input) 1.9 2.1 2.4 2.8 ns t hckl input high to low (pad to r-cell input) 1.9 2.1 2.4 2.8 ns t hpwh minimum pulse width high 1.4 1.6 1.8 2.1 ns t hpwl minimum pulse width low 1.4 1.6 1.8 2.1 ns t hcksw maximum skew 0.3 0.4 0.4 0.5 ns t hp minimum period 2.7 3.1 3.6 4.2 ns f hmax maximum frequency 350 320 280 240 mhz routed array clock networks t rckh input low to high (light load) (pad to r-cell input) 2.4 2.7 3.0 3.5 ns t rckl input high to low (light load) (pad to r-cell input) 2.4 2.7 3.1 3.6 ns t rckh input low to high (50% load) (pad to r-cell input) 2.7 3.0 3.5 4.1 ns t rckl input high to low (50% load) (pad to r-cell input) 2.7 3.1 3.6 4.2 ns t rckh input low to high (100% load) (pad to r-cell input) 2.7 3.1 3.5 4.1 ns t rckl input high to low (100% load) (pad to r-cell input) 2.8 3.2 3.6 4.3 ns t rpwh min. pulse width high 2.1 2.4 2.7 3.2 ns t rpwl min. pulse width low 2.1 2.4 2.7 3.2 ns t rcksw maximum skew (light load) 0.85 0.98 1.1 1.3 ns t rcksw maximum skew (50% load) 1.23 1.4 1.6 1.9 ns t rcksw maximum skew (100% load) 1.30 1.5 1.7 2.0 ns ttl output module timing 1 t dlh data-to-pad low to high 1.6 1.9 2.1 2.5 ns t dhl data-to-pad high to low 1.6 1.9 2.1 2.5 ns t enzl enable-to-pad, z to l 2.1 2.4 2.8 3.2 ns t enzh enable-to-pad, z to h 2.3 2.7 3.1 3.6 ns t enlz enable-to-pad, l to z 1.4 1.7 1.9 2.2 ns t enhz enable-to-pad, h to z 1.3 1.5 1.7 2.0 ns note: 1. delays based on 35pf loading, except t enzl and t enzh . for t enzl and t enzh the loading is 5pf.
34 pin description clka/b clock a and b these pins are 3.3v/5.0v pci/ttl clock inputs for clock distribution networks. the clock input is buffered prior to clocking the r-cells. if not used, this pin must be set low or high on the board. it must not be left floating. (for a54sx72a, these clocks can be configured as bidirectional.) gnd ground low supply voltage. hclk dedicated (hard-wired) array clock this pin is the 3.3v/5.0v pci/ttl clock input for sequential modules. this input is directly wired to each r-cell and offers clock speeds independent of the number of r-cells being driven. if not used, this pin must be set low or high on the board. it must not be left floating. i/o input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. based on certain configurations, input and output levels are compatible with standard ttl, lvttl, 3.3v pci or 5.0v pci specifications. unused i/o pins are automatically tristated by the designer series software. nc no connection this pin is not connected to circuitry within the device. pra, i/o probe a the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when verification has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb, i/o probe b the probe b pin is used to output data from any node within the device. this diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when verification has been completed. the pin ? s probe capabilities can be permanently disabled to protect programmed design confidentiality. tck test clock test clock input for diagnostic probe and device programming. in flexible mode, tck becomes active when the tms pin is set low (refer to table 2 on page 8 ). this pin functions as an i/o when the boundary scan state machine reaches the ? logic reset ? state. tdi test data input serial input for boundary scan testing and diagnostic probe. in flexible mode, tdi is active when the tms pin is set low (refer to table 2 on page 8 ). this pin functions as an i/o when the boundary scan state machine reaches the ? logic reset ? state. tdo test data output serial output for boundary scan testing. in flexible mode, tdo is active when the tms pin is set low (refer to table 2 on page 8 ). this pin functions as an i/o when the boundary scan state machine reaches the ? logic reset ? state. tms test mode select the tms pin controls the use of the ieee 1149.1 boundary scan pins (tck, tdi, tdo). in flexible mode when the tms pin is set low, the tck, tdi, and tdo pins are boundary scan pins (refer to table 2 on page 8 ). once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the ? logic reset ? state. at this point, the boundary scan pins will be released and will function as regular i/o pins. the ? logic reset ? state is reached 5 tck cycles after the tms pin is set high. in dedicated test mode, tms functions as specified in the ieee 1149.1 specifications. v cci supply voltage supply voltage for i/os. see table 1 on page 8 . v cca supply voltage supply voltage for array. see table 1 on page 8 . v ccr supply voltage supply voltage for input tolerance (required for internal biasing) see table 1 on page 8 .
35 54sx family fpgas package pin assignments 84-pin plcc (top view) 184 84-pin plcc
36 84-pin plcc package pin number a54sx08 function pin number a54sx08 function 1v ccr 43 v ccr 2 gnd 44 i/o 3v cca 45 hclk 4 pra, i/o 46 i/o 5 i/o 47 i/o 6 i/o 48 i/o 7v cci 49 i/o 8 i/o 50 i/o 9 i/o 51 i/o 10 i/o 52 tdo, i/o 11 tck, i/o 53 i/o 12 tdi, i/o 54 i/o 13 i/o 55 i/o 14 i/o 56 i/o 15 i/o 57 i/o 16 tms 58 i/o 17 i/o 59 v cca 18 i/o 60 v cci 19 i/o 61 gnd 20 i/o 62 i/o 21 i/o 63 i/o 22 i/o 64 i/o 23 i/o 65 i/o 24 i/o 66 i/o 25 i/o 67 i/o 26 i/o 68 v cca 27 gnd 69 gnd 28 v cci 70 i/o 29 i/o 71 i/o 30 i/o 72 i/o 31 i/o 73 i/o 32 i/o 74 i/o 33 i/o 75 i/o 34 i/o 76 i/o 35 i/o 77 i/o 36 i/o 78 i/o 37 i/o 79 i/o 38 i/o 80 i/o 39 i/o 81 i/o 40 prb, i/o 82 i/o 41 v cca 83 clka 42 gnd 84 clkb
54sx family fpgas 37 package pin assignments (continued) 208-pin pqfp (top view) 208-pin pqfp 1 208
38 208-pin pqfp pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function 1 gnd gnd gnd 54 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 55 i/o i/o i/o 3 i/o i/o i/o 56 i/o i/o i/o 4 nc i/o i/o 57 i/o i/o i/o 5 i/o i/o i/o 58 i/o i/o i/o 6 nc i/o i/o 59 i/o i/o i/o 7 i/o i/o i/o 60 v cci v cci v cci 8 i/o i/o i/o 61 nc i/o i/o 9 i/o i/o i/o 62 i/o i/o i/o 10 i/o i/o i/o 63 i/o i/o i/o 11 tms tms tms 64 nc i/o i/o 12 v cci v cci v cci 65* i/o i/o nc* 13 i/o i/o i/o 66 i/o i/o i/o 14 nc i/o i/o 67 nc i/o i/o 15 i/o i/o i/o 68 i/o i/o i/o 16 i/o i/o i/o 69 i/o i/o i/o 17 nc i/o i/o 70 nc i/o i/o 18 i/o i/o i/o 71 i/o i/o i/o 19 i/o i/o i/o 72 i/o i/o i/o 20 nc i/o i/o 73 nc i/o i/o 21 i/o i/o i/o 74 i/o i/o i/o 22 i/o i/o i/o 75 nc i/o i/o 23 nc i/o i/o 76 prb, i/o prb, i/o prb, i/o 24 i/o i/o i/o 77 gnd gnd gnd 25 v ccr v ccr v ccr 78 v cca v cca v cca 26 gnd gnd gnd 79 gnd gnd gnd 27 v cca v cca v cca 80 v ccr v ccr v ccr 28 gnd gnd gnd 81 i/o i/o i/o 29 i/o i/o i/o 82 hclk hclk hclk 30 i/o i/o i/o 83 i/o i/o i/o 31 nc i/o i/o 84 i/o i/o i/o 32 i/o i/o i/o 85 nc i/o i/o 33 i/o i/o i/o 86 i/o i/o i/o 34 i/o i/o i/o 87 i/o i/o i/o 35 nc i/o i/o 88 nc i/o i/o 36 i/o i/o i/o 89 i/o i/o i/o 37 i/o i/o i/o 90 i/o i/o i/o 38 i/o i/o i/o 91 nc i/o i/o 39 nc i/o i/o 92 i/o i/o i/o 40 v cci v cci v cci 93 i/o i/o i/o 41 v cca v cca v cca 94 nc i/o i/o 42 i/o i/o i/o 95 i/o i/o i/o 43 i/o i/o i/o 96 i/o i/o i/o 44 i/o i/o i/o 97 nc i/o i/o 45 i/o i/o i/o 98 v cci v cci v cci 46 i/o i/o i/o 99 i/o i/o i/o 47 i/o i/o i/o 100 i/o i/o i/o 48 nc i/o i/o 101 i/o i/o i/o 49 i/o i/o i/o 102 i/o i/o i/o 50 nc i/o i/o 103 tdo, i/o tdo, i/o tdo, i/o 51 i/o i/o i/o 104 i/o i/o i/o 52 gnd gnd gnd 105 gnd gnd gnd 53 i/o i/o i/o 106 nc i/o i/o * please note that pin 65 in the a54sx32 ? pq208 is a no connect (nc).
54sx family fpgas 39 107 i/o i/o i/o 158 i/o i/o i/o 108 nc i/o i/o 159 i/o i/o i/o 109 i/o i/o i/o 160 i/o i/o i/o 110 i/o i/o i/o 161 i/o i/o i/o 111 i/o i/o i/o 162 i/o i/o i/o 112 i/o i/o i/o 163 i/o i/o i/o 113 i/o i/o i/o 164 v cci v cci v cci 114 v cca v cca v cca 165 i/o i/o i/o 115 v cci v cci v cci 166 i/o i/o i/o 116 nc i/o i/o 167 nc i/o i/o 117 i/o i/o i/o 168 i/o i/o i/o 118 i/o i/o i/o 169 i/o i/o i/o 119 nc i/o i/o 170 nc i/o i/o 120 i/o i/o i/o 171 i/o i/o i/o 121 i/o i/o i/o 172 i/o i/o i/o 122 nc i/o i/o 173 nc i/o i/o 123 i/o i/o i/o 174 i/o i/o i/o 124 i/o i/o i/o 175 i/o i/o i/o 125 nc i/o i/o 176 nc i/o i/o 126 i/o i/o i/o 177 i/o i/o i/o 127 i/o i/o i/o 178 i/o i/o i/o 128 i/o i/o i/o 179 i/o i/o i/o 129 gnd gnd gnd 180 clka clka clka 130 v cca v cca v cca 181 clkb clkb clkb 131 gnd gnd gnd 182 v ccr v ccr v ccr 132 v ccr v ccr v ccr 183 gnd gnd gnd 133 i/o i/o i/o 184 v cca v cca v cca 134 i/o i/o i/o 185 gnd gnd gnd 135 nc i/o i/o 186 pra, i/o pra, i/o pra, i/o 136 i/o i/o i/o 187 i/o i/o i/o 137 i/o i/o i/o 188 i/o i/o i/o 138 nc i/o i/o 189 nc i/o i/o 139 i/o i/o i/o 190 i/o i/o i/o 140 i/o i/o i/o 191 i/o i/o i/o 141 nc i/o i/o 192 nc i/o i/o 142 i/o i/o i/o 193 i/o i/o i/o 143 nc i/o i/o 194 i/o i/o i/o 144 i/o i/o i/o 195 nc i/o i/o 145 v cca v cca v cca 196 i/o i/o i/o 146 gnd gnd gnd 197 i/o i/o i/o 147 i/o i/o i/o 198 nc i/o i/o 148 v cci v cci v cci 199 i/o i/o i/o 149 i/o i/o i/o 200 i/o i/o i/o 150 i/o i/o i/o 201 v cci v cci v cci 151 i/o i/o i/o 202 nc i/o i/o 152 i/o i/o i/o 203 nc i/o i/o 153 i/o i/o i/o 204 i/o i/o i/o 154 i/o i/o i/o 205 nc i/o i/o 155 nc i/o i/o 206 i/o i/o i/o 156 nc i/o i/o 207 i/o i/o i/o 157 gnd gnd gnd 208 tck, i/o tck, i/o tck, i/o 208-pin pqfp (continued) pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function * please note that pin 65 in the a54sx32 ? pq208 is a no connect (nc).
40 package pin assignments (continued) 144-pin tqfp (top view) 1 144 144-pin tqfp
54sx family fpgas 41 144-pin tqfp pin number a54sx08 function a54sx16p function a54sx32 function pin number a54sx08 function a54sx16p function a54sx32 function 1 gnd gnd gnd 41 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 42 i/o i/o i/o 3 i/o i/o i/o 43 i/o i/o i/o 4 i/o i/o i/o 44 v cci v cci v cci 5 i/o i/o i/o 45 i/o i/o i/o 6 i/o i/o i/o 46 i/o i/o i/o 7 i/o i/o i/o 47 i/o i/o i/o 8 i/o i/o i/o 48 i/o i/o i/o 9 tms tms tms 49 i/o i/o i/o 10 v cci v cci v cci 50 i/o i/o i/o 11 gnd gnd gnd 51 i/o i/o i/o 12 i/o i/o i/o 52 i/o i/o i/o 13 i/o i/o i/o 53 i/o i/o i/o 14 i/o i/o i/o 54 prb, i/o prb, i/o prb, i/o 15 i/o i/o i/o 55 i/o i/o i/o 16 i/o i/o i/o 56 v cca v cca v cca 17 i/o i/o i/o 57 gnd gnd gnd 18 i/o i/o i/o 58 v ccr v ccr v ccr 19 v ccr v ccr v ccr 59 i/o i/o i/o 20 v cca v cca v cca 60 hclk hclk hclk 21 i/o i/o i/o 61 i/o i/o i/o 22 i/o i/o i/o 62 i/o i/o i/o 23 i/o i/o i/o 63 i/o i/o i/o 24 i/o i/o i/o 64 i/o i/o i/o 25 i/o i/o i/o 65 i/o i/o i/o 26 i/o i/o i/o 66 i/o i/o i/o 27 i/o i/o i/o 67 i/o i/o i/o 28 gnd gnd gnd 68 v cci v cci v cci 29 v cci v cci v cci 69 i/o i/o i/o 30 v cca v cca v cca 70 i/o i/o i/o 31 i/o i/o i/o 71 tdo, i/o tdo, i/o tdo, i/o 32 i/o i/o i/o 72 i/o i/o i/o 33 i/o i/o i/o 73 gnd gnd gnd 34 i/o i/o i/o 74 i/o i/o i/o 35 i/o i/o i/o 75 i/o i/o i/o 36 gnd gnd gnd 76 i/o i/o i/o 37 i/o i/o i/o 77 i/o i/o i/o 38 i/o i/o i/o 78 i/o i/o i/o 39 i/o i/o i/o 79 v cca v cca v cca 40 i/o i/o i/o 80 v cci v cci v cci
42 81 gnd gnd gnd 113 i/o i/o i/o 82 i/o i/o i/o 114 i/o i/o i/o 83 i/o i/o i/o 115 v cci v cci v cci 84 i/o i/o i/o 116 i/o i/o i/o 85 i/o i/o i/o 117 i/o i/o i/o 86 i/o i/o i/o 118 i/o i/o i/o 87 i/o i/o i/o 119 i/o i/o i/o 88 i/o i/o i/o 120 i/o i/o i/o 89 v cca v cca v cca 121 i/o i/o i/o 90 v ccr v ccr v ccr 122 i/o i/o i/o 91 i/o i/o i/o 123 i/o i/o i/o 92 i/o i/o i/o 124 i/o i/o i/o 93 i/o i/o i/o 125 clka clka clka 94 i/o i/o i/o 126 clkb clkb clkb 95 i/o i/o i/o 127 v ccr v ccr v ccr 96 i/o i/o i/o 128 gnd gnd gnd 97 i/o i/o i/o 129 v cca v cca v cca 98 v cca v cca v cca 130 i/o i/o i/o 99 gnd gnd gnd 131 pra, i/o pra, i/o pra, i/o 100 i/o i/o i/o 132 i/o i/o i/o 101 gnd gnd gnd 133 i/o i/o i/o 102 v cci v cci v cci 134 i/o i/o i/o 103 i/o i/o i/o 135 i/o i/o i/o 104 i/o i/o i/o 136 i/o i/o i/o 105 i/o i/o i/o 137 i/o i/o i/o 106 i/o i/o i/o 138 i/o i/o i/o 107 i/o i/o i/o 139 i/o i/o i/o 108 i/o i/o i/o 140 v cci v cci v cci 109 gnd gnd gnd 141 i/o i/o i/o 110 i/o i/o i/o 142 i/o i/o i/o 111 i/o i/o i/o 143 i/o i/o i/o 112 i/o i/o i/o 144 tck, i/o tck, i/o tck, i/o 113 i/o i/o i/o 144-pin tqfp (continued) pin number a54sx08 function a54sx16p function a54sx32 function pin number a54sx08 function a54sx16p function a54sx32 function
54sx family fpgas 43 package pin assignments (continued) 176-pin tqfp (top view) 176-pin tqfp 176 1
44 176-pin tqfp pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function 1 gnd gnd gnd 45 i/o i/o i/o 2 tdi, i/o tdi, i/o tdi, i/o 46 i/o i/o i/o 3 nc i/o i/o 47 i/o i/o i/o 4 i/o i/o i/o 48 i/o i/o i/o 5 i/o i/o i/o 49 i/o i/o i/o 6 i/o i/o i/o 50 i/o i/o i/o 7 i/o i/o i/o 51 i/o i/o i/o 8 i/o i/o i/o 52 v cci v cci v cci 9 i/o i/o i/o 53 i/o i/o i/o 10 tms tms tms 54 nc i/o i/o 11 v cci v cci v cci 55 i/o i/o i/o 12 nc i/o i/o 56 i/o i/o i/o 13 i/o i/o i/o 57 nc i/o i/o 14 i/o i/o i/o 58 i/o i/o i/o 15 i/o i/o i/o 59 i/o i/o i/o 16 i/o i/o i/o 60 i/o i/o i/o 17 i/o i/o i/o 61 i/o i/o i/o 18 i/o i/o i/o 62 i/o i/o i/o 19 i/o i/o i/o 63 i/o i/o i/o 20 i/o i/o i/o 64 prb, i/o prb, i/o prb, i/o 21 gnd gnd gnd 65 gnd gnd gnd 22 v cca v cca v cca 66 v cca v cca v cca 23 gnd gnd gnd 67 v ccr v ccr v ccr 24 i/o i/o i/o 68 i/o i/o i/o 25 i/o i/o i/o 69 hclk hclk hclk 26 i/o i/o i/o 70 i/o i/o i/o 27 i/o i/o i/o 71 i/o i/o i/o 28 i/o i/o i/o 72 i/o i/o i/o 29 i/o i/o i/o 73 i/o i/o i/o 30 i/o i/o i/o 74 i/o i/o i/o 31 i/o i/o i/o 75 i/o i/o i/o 32 v cci v cci v cci 76 i/o i/o i/o 33 v cca v cca v cca 77 i/o i/o i/o 34 i/o i/o i/o 78 i/o i/o i/o 35 i/o i/o i/o 79 nc i/o i/o 36 i/o i/o i/o 80 i/o i/o i/o 37 i/o i/o i/o 81 nc i/o i/o 38 i/o i/o i/o 82 v cci v cci v cci 39 i/o i/o i/o 83 i/o i/o i/o 40 nc i/o i/o 84 i/o i/o i/o 41 i/o i/o i/o 85 i/o i/o i/o 42 nc i/o i/o 86 i/o i/o i/o 43 i/o i/o i/o 87 tdo, i/o tdo, i/o tdo, i/o 44 gnd gnd gnd 88 i/o i/o i/o
54sx family fpgas 45 89 gnd gnd gnd 133 gnd gnd gnd 90 nc i/o i/o 134 i/o i/o i/o 91 nc i/o i/o 135 i/o i/o i/o 92 i/o i/o i/o 136 i/o i/o i/o 93 i/o i/o i/o 137 i/o i/o i/o 94 i/o i/o i/o 138 i/o i/o i/o 95 i/o i/o i/o 139 i/o i/o i/o 96 i/o i/o i/o 140 v cci v cci v cci 97 i/o i/o i/o 141 i/o i/o i/o 98 v cca v cca v cca 142 i/o i/o i/o 99 v cci v cci v cci 143 i/o i/o i/o 100 i/o i/o i/o 144 i/o i/o i/o 101 i/o i/o i/o 145 i/o i/o i/o 102 i/o i/o i/o 146 i/o i/o i/o 103 i/o i/o i/o 147 i/o i/o i/o 104 i/o i/o i/o 148 i/o i/o i/o 105 i/o i/o i/o 149 i/o i/o i/o 106 i/o i/o i/o 150 i/o i/o i/o 107 i/o i/o i/o 151 i/o i/o i/o 108 gnd gnd gnd 152 clka clka clka 109 v cca v cca v cca 153 clkb clkb clkb 110 gnd gnd gnd 154 v ccr v ccr v ccr 111 i/o i/o i/o 155 gnd gnd gnd 112 i/o i/o i/o 156 v cca v cca v cca 113 i/o i/o i/o 157 pra, i/o pra, i/o pra, i/o 114 i/o i/o i/o 158 i/o i/o i/o 115 i/o i/o i/o 159 i/o i/o i/o 116 i/o i/o i/o 160 i/o i/o i/o 117 i/o i/o i/o 161 i/o i/o i/o 118 nc i/o i/o 162 i/o i/o i/o 119 i/o i/o i/o 163 i/o i/o i/o 120 nc i/o i/o 164 i/o i/o i/o 121 nc i/o i/o 165 i/o i/o i/o 122 v cca v cca v cca 166 i/o i/o i/o 123 gnd gnd gnd 167 i/o i/o i/o 124 v cci v cci v cci 168 nc i/o i/o 125 i/o i/o i/o 169 v cci v cci v cci 126 i/o i/o i/o 170 i/o i/o i/o 127 i/o i/o i/o 171 nc i/o i/o 128 i/o i/o i/o 172 nc i/o i/o 129 i/o i/o i/o 173 nc i/o i/o 130 i/o i/o i/o 174 i/o i/o i/o 131 nc i/o i/o 175 i/o i/o i/o 132 nc i/o i/o 176 tck, i/o tck, i/o tck, i/o 176-pin tqfp (continued) pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function pin number a54sx08 function a54sx16, a54sx16p function a54sx32 function
46 package pin assignments (continued) 100-pin vqfp (top view) 1 100-pin vqfp 100
54sx family fpgas 47 100-vqfp pin number a54sx08 function a54sx16, a54sx16p function pin number a54sx08 function a54sx16 a54sx16p function 1 gnd gnd 51 gnd gnd 2 tdi, i/o tdi, i/o 52 i/o i/o 3 i/o i/o 53 i/o i/o 4 i/o i/o 54 i/o i/o 5 i/o i/o 55 i/o i/o 6 i/o i/o 56 i/o i/o 7tmstms 57v cca v cca 8v cci v cci 58 v cci v cci 9 gnd gnd 59 i/o i/o 10 i/o i/o 60 i/o i/o 11 i/o i/o 61 i/o i/o 12 i/o i/o 62 i/o i/o 13 i/o i/o 63 i/o i/o 14 i/o i/o 64 i/o i/o 15 i/o i/o 65 i/o i/o 16 i/o i/o 66 i/o i/o 17 i/o i/o 67 v cca v cca 18 i/o i/o 68 gnd gnd 19 i/o i/o 69 gnd gnd 20 v cci v cci 70 i/o i/o 21 i/o i/o 71 i/o i/o 22 i/o i/o 72 i/o i/o 23 i/o i/o 73 i/o i/o 24 i/o i/o 74 i/o i/o 25 i/o i/o 75 i/o i/o 26 i/o i/o 76 i/o i/o 27 i/o i/o 77 i/o i/o 28 i/o i/o 78 i/o i/o 29 i/o i/o 79 i/o i/o 30 i/o i/o 80 i/o i/o 31 i/o i/o 81 i/o i/o 32 i/o i/o 82 v cci v cci 33 i/o i/o 83 i/o i/o 34 prb, i/o prb, i/o 84 i/o i/o 35 v cca v cca 85 i/o i/o 36 gnd gnd 86 i/o i/o 37 v ccr v ccr 87 clka clka 38 i/o i/o 88 clkb clkb 39 hclk hclk 89 v ccr v ccr 40 i/o i/o 90 v cca v cca 41 i/o i/o 91 gnd gnd 42 i/o i/o 92 pra, i/o pra, i/o 43 i/o i/o 93 i/o i/o 44 v cci v cci 94 i/o i/o 45 i/o i/o 95 i/o i/o 46 i/o i/o 96 i/o i/o 47 i/o i/o 97 i/o i/o 48 i/o i/o 98 i/o i/o 49 tdo, i/o tdo, i/o 99 i/o i/o 50 i/o i/o 100 tck, i/o tck, i/o
48 package pin assignments (continued) 313-pin pbga (top view) 1 2345 6789101112131415 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae 16 17 18 19 20 21 22 23 24 25 1 2345 678910111213141516171819202122232425
54sx family fpgas 49 313-pin pbga pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function a1 gnd ac15 i/o c5 nc f20 i/o a3 nc ac17 i/o c7 i/o f22 i/o a5 i/o ac19 i/o c9 i/o f24 i/o a7 i/o ac21 i/o c11 i/o g1 i/o a9 i/o ac23 i/o c13 v cci g3 tms a11 i/o ac25 nc c15 i/o g5 i/o a13 v ccr ad2 gnd c17 i/o g7 i/o a15 i/o ad4 i/o c19 v cci g9 v cci a17 i/o ad6 v cci c21 i/o g11 i/o a19 i/o ad8 i/o c23 i/o g13 clkb a21 i/o ad10 i/o c25 nc g15 i/o a23 nc ad12 prb, i/o d2 i/o g17 i/o a25 gnd ad14 i/o d4 nc g19 i/o aa1 i/o ad16 i/o d6 i/o g21 i/o aa3 i/o ad18 i/o d8 i/o g23 i/o aa5 nc ad20 i/o d10 i/o g25 i/o aa7 i/o ad22 nc d12 i/o h2 i/o aa9 nc ad24 i/o d14 i/o h4 i/o aa11 i/o ae1 nc d16 i/o h6 i/o aa13 i/o ae3 i/o d18 i/o h8 i/o aa15 i/o ae5 i/o d20 i/o h10 i/o aa17 i/o ae7 i/o d22 i/o h12 pra, i/o aa19 i/o ae9 i/o d24 nc h14 i/o aa21 i/o ae11 i/o e1 i/o h16 i/o aa23 nc ae13 v cca e3 nc h18 nc aa25 i/o ae15 i/o e5 i/o h20 i/o ab2 nc ae17 i/o e7 i/o h22 v cci ab4 nc ae19 i/o e9 i/o h24 i/o ab6 i/o ae21 i/o e11 i/o j1 i/o ab8 i/o ae23 tdo, i/o e13 v cca j3 i/o ab10 i/o ae25 gnd e15 i/o j5 i/o ab12 i/o b2 tck, i/o e17 i/o j7 nc ab14 i/o b4 i/o e19 i/o j9 i/o ab16 i/o b6 i/o e21 i/o j11 i/o ab18 v cci b8 i/o e23 i/o j13 clka ab20 nc b10 i/o e25 i/o j15 i/o ab22 i/o b12 i/o f2 i/o j17 i/o ab24 i/o b14 i/o f4 i/o j19 i/o ac1 i/o b16 i/o f6 nc j21 gnd ac3 i/o b18 i/o f8 i/o j23 i/o ac5 i/o b20 i/o f10 nc j25 i/o ac7 i/o b22 i/o f12 i/o k2 i/o ac9 i/o b24 i/o f14 i/o k4 i/o ac11 i/o c1 tdi, i/o f16 nc k6 i/o ac13 v ccr c3 i/o f18 i/o k8 v cci
50 k10 i/o n3 v cca r21 i/o v18 i/o k12 i/o n5 v ccr r23 i/o v20 i/o k14 i/o n7 i/o r25 i/o v22 v cca k16 i/o n9 v cci t2 i/o v24 v cci k18 i/o n11 gnd t4 i/o w1 i/o k20 v cca n13 gnd t6 i/o w3 i/o k22 i/o n15 gnd t8 i/o w5 i/o k24 i/o n17 i/o t10 i/o w7 nc l1 i/o n19 i/o t12 i/o w9 i/o l3 i/o n21 i/o t14 hclk w11 i/o l5 i/o n23 v ccr t16 i/o w13 v cci l7 i/o n25 v cca t18 i/o w15 i/o l9 i/o p2 i/o t20 i/o w17 i/o l11 i/o p4 i/o t22 i/o w19 i/o l13 gnd p6 i/o t24 i/o w21 i/o l15 i/o p8 i/o u1 i/o w23 i/o l17 i/o p10 i/o u3 i/o w25 i/o l19 i/o p12 gnd u5 v cci y2 i/o l21 i/o p14 gnd u7 i/o y4 i/o l23 i/o p16 i/o u9 i/o y6 i/o l25 i/o p18 i/o u15 i/o y8 i/o m2 i/o p20 nc u17 i/o y10 i/o m4 i/o p22 i/o u19 i/o y12 i/o m6 i/o p24 i/o u21 i/o y14 i/o m8 i/o r1 i/o u23 i/o y16 i/o m10 i/o r3 i/o u25 i/o y18 i/o m12 gnd r5 i/o v2 v cca y20 nc m14 gnd r7 i/o v4 i/o y22 i/o m16 v cci r9 i/o v6 i/o y24 nc m18 i/o r11 i/o v8 i/o m20 i/o r13 gnd v10 i/o m22 i/o r15 i/o v12 i/o m24 i/o r17 i/o v14 i/o n1 i/o r19 i/o v16 nc 313-pin pbga (continued) pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function
54sx family fpgas 51 package pin assignments (continued) 329-pin pbga (top view) 23 22 21 20 19 18 17 16 15 14 10 11 12 13 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac
52 329-pin pbga pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function a1 gnd aa23 v cci ac22 v cci c21 v cci a2 gnd ab1 i/o ac23 gnd c22 gnd a3 v cci ab2 gnd b1 v cci c23 nc a4 nc ab3 i/o b2 gnd d1 i/o a5 i/o ab4 i/o b3 i/o d2 i/o a6 i/o ab5 i/o b4 i/o d3 i/o a7 v cci ab6 i/o b5 i/o d4 tck, i/o a8 nc ab7 i/o b6 i/o d5 i/o a9 i/o ab8 i/o b7 i/o d6 i/o a10 i/o ab9 i/o b8 i/o d7 i/o a11 i/o ab10 i/o b9 i/o d8 i/o a12 i/o ab11 prb, i/o b10 i/o d9 i/o a13 clkb ab12 i/o b11 i/o d10 i/o a14 i/o ab13 hclk b12 pra, i/o d11 v cca a15 i/o ab14 i/o b13 clka d12 v ccr a16 i/o ab15 i/o b14 i/o d13 i/o a17 i/o ab16 i/o b15 i/o d14 i/o a18 i/o ab17 i/o b16 i/o d15 i/o a19 i/o ab18 i/o b17 i/o d16 i/o a20 i/o ab19 i/o b18 i/o d17 i/o a21 nc ab20 i/o b19 i/o d18 i/o a22 v cci ab21 i/o b20 i/o d19 i/o a23 gnd ab22 gnd b21 i/o d20 i/o aa1 v cci ab23 i/o b22 gnd d21 i/o aa2 i/o ac1 gnd b23 v cci d22 i/o aa3 gnd ac2 v cci c1 nc d23 i/o aa4 i/o ac3 nc c2 tdi, i/o e1 v cci aa5 i/o ac4 i/o c3 gnd e2 i/o aa6 i/o ac5 i/o c4 i/o e3 i/o aa7 i/o ac6 i/o c5 i/o e4 i/o aa8 i/o ac7 i/o c6 i/o e20 i/o aa9 i/o ac8 i/o c7 i/o e21 i/o aa10 i/o ac9 v cci c8 i/o e22 i/o aa11 i/o ac10 i/o c9 i/o e23 i/o aa12 i/o ac11 i/o c10 i/o f1 i/o aa13 i/o ac12 i/o c11 i/o f2 tms aa14 i/o ac13 i/o c12 i/o f3 i/o aa15 i/o ac14 i/o c13 i/o f4 i/o aa16 i/o ac15 nc c14 i/o f20 i/o aa17 i/o ac16 i/o c15 i/o f21 i/o aa18 i/o ac17 i/o c16 i/o f22 i/o aa19 i/o ac18 i/o c17 i/o f23 i/o aa20 tdo, i/o ac19 i/o c18 i/o g1 i/o aa21 v cci ac20 i/o c19 i/o g2 i/o aa22 i/o ac21 nc c20 i/o g3 i/o
54sx family fpgas 53 g4 i/o l22 i/o r20 i/o y10 i/o g20 i/o l23 nc r21 i/o y11 i/o g21 i/o m1 i/o r22 i/o y12 v cca g22 i/o m2 i/o r23 i/o y13 v ccr g23 gnd m3 i/o t1 i/o y14 i/o h1 i/o m4 v cca t2 i/o y15 i/o h2 i/o m10 gnd t3 i/o y16 i/o h3 i/o m11 gnd t4 i/o y17 i/o h4 i/o m12 gnd t20 i/o y18 i/o h20 v cca m13 gnd t21 i/o y19 i/o h21 i/o m14 gnd t22 i/o y20 gnd h22 i/o m20 v cca t23 i/o y21 i/o h23 i/o m21 i/o u1 i/o y22 i/o j1 nc m22 i/o u2 i/o y23 i/o j2 i/o m23 v cci u3 v cca j3 i/o n1 i/o u4 i/o j4 i/o n2 i/o u20 i/o j20 i/o n3 i/o u21 v cca j21 i/o n4 i/o u22 i/o j22 i/o n10 gnd u23 i/o j23 i/o n11 gnd v1 v cci k1 i/o n12 gnd v2 i/o k2 i/o n13 gnd v3 i/o k3 i/o n14 gnd v4 i/o k4 i/o n20 nc v20 i/o k10 gnd n21 i/o v21 i/o k11 gnd n22 i/o v22 i/o k12 gnd n23 i/o v23 i/o k13 gnd p1 i/o w1 i/o k14 gnd p2 i/o w2 i/o k20 i/o p3 i/o w3 i/o k21 i/o p4 i/o w4 i/o k22 i/o p10 gnd w20 i/o k23 i/o p11 gnd w21 i/o l1 i/o p12 gnd w22 i/o l2 i/o p13 gnd w23 nc l3 i/o p14 gnd y1 nc l4 v ccr p20 i/o y2 i/o l10 gnd p21 i/o y3 i/o l11 gnd p22 i/o y4 gnd l12 gnd p23 i/o y5 i/o l13 gnd r1 i/o y6 i/o l14 gnd r2 i/o y7 i/o l20 v ccr r3 i/o y8 i/o l21 i/o r4 i/o y9 i/o 329-pin pbga pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function pin number a54sx32 function
54 package pin assignments (continued) 144-pin fbga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m
55 54sx family fpgas 144-pin fbga pin number a54sx08 function pin number a54sx08 function pin number a54sx08 function a1 i/o e1 i/o j1 i/o a2 i/o e2 i/o j2 i/o a3 i/o e3 i/o j3 i/o a4 i/o e4 i/o j4 i/o a5 v cca e5 tms j5 i/o a6 gnd e6 v cci j6 prb, i/o a7 clka e7 v cci j7 i/o a8 i/o e8 v cci j8 i/o a9 i/o e9 v cca j9 i/o a10 i/o e10 i/o j10 i/o a11 i/o e11 gnd j11 i/o a12 i/o e12 i/o j12 v cca b1 i/o f1 i/o k1 i/o b2 gnd f2 i/o k2 i/o b3 i/o f3 v ccr k3 i/o b4 i/o f4 i/o k4 i/o b5 i/o f5 gnd k5 i/o b6 i/o f6 gnd k6 i/o b7 clkb f7 gnd k7 gnd b8 i/o f8 v cci k8 i/o b9 i/o f9 i/o k9 i/o b10 i/o f10 gnd k10 gnd b11 gnd f11 i/o k11 i/o b12 i/o f12 i/o k12 i/o c1 i/o g1 i/o l1 gnd c2 i/o g2 gnd l2 i/o c3 tck, i/o g3 i/o l3 i/o c4 i/o g4 i/o l4 i/o c5 i/o g5 gnd l5 i/o c6 pra, i/o g6 gnd l6 i/o c7 i/o g7 gnd l7 hclk c8 i/o g8 v cci l8 i/o c9 i/o g9 i/o l9 i/o c10 i/o g10 i/o l10 i/o c11 i/o g11 i/o l11 i/o c12 i/o g12 i/o l12 i/o d1 i/o h1 i/o m1 i/o d2 v cci h2 i/o m2 i/o d3 tdi, i/o h3 i/o m3 i/o d4 i/o h4 i/o m4 i/o d5 i/o h5 v cca m5 i/o d6 i/o h6 v cca m6 i/o d7 i/o h7 v cci m7 v cca d8 i/o h8 v cci m8 i/o d9 i/o h9 v cca m9 i/o d10 i/o h10 i/o m10 i/o d11 i/o h11 i/o m11 tdo, i/o d12 i/o h12 v ccr m12 i/o
56 package mechanical drawings plastic leaded chip carrier (plcc) e3 e1 e d d1 d3 .048 (1.219) .042 (1.067) e1 .049 (1.244) a 0.006 a1 .032 (0.812) max b2 b c .075 (1.905) max .020 (0.508) min .044 (1.117) .035 rad (0.889) .005 (0.127) after lead finish base line d2/e2
54sx family fpgas 57 notes: 1. all dimensions are in millimeters. 2. bsc ? basic spacing between centers. plastic leaded chip carrier packages (plcc) jedec equiv plcc 84 ms007 ae var dimension min. max a 3.94 4.45 a1 2.29 3.30 b 0.33 0.69 b2 0.66 0.81 c 0.13 0.28 d/e 29.72 30.73 d1/e1 28.96 29.46 d2/e2 27.69 28.70 d3/e3 25.4 nominal e1 1.27 bsc
58 package mechanical drawings (continued) plastic quad flat pack (pqfp, tqfp, vqfp) e e1 d d1 a2 a l a1 10 typ theta 0.20 rad typ 0.20 rad typ b e detail a see detail a c ccc
54sx family fpgas 59 package mechanical drawings (continued) plastic quad flat pack rectangular package (pqfp) e e1 d d1 a2 a l a1 10 typ theta 0.20 rad typ 0.20 rad typ b e detail a see detail a c ccc
60 plastic quad flat packs (pqfp) jedec equiv pqfp 208 mo-143 dimension min. nom max a 3.70 4.10 a1 0.25 0.38 a2 3.20 3.40 3.60 b 0.17 0.27 c 0.09 0.20 d/e 30.25 30.60 30.85 d1/e1 27.90 28.00 28.10 e0.50 bsc l 0.50 0.60 0.75 ccc 0.10 theta 0 7 deg diameter 19.82 20.32 20.82 thin quad flat packs (tqfp) jedec equiv tqfp 144 mo-136 tqfp 176 mo-136 dimension min. nom max min nom max a 1.60 1.60 a1 0.05 0.10 0.15 0.05 0.10 0.15 a2 1.35 1.40 1.45 1.35 1.40 1.45 b 0.17 0.27 0.17 0.27 c 0.09 0.20 0.09 0.20 d/e 21.75 22.00 22.25 25.75 26.00 26.25 d1/e1 19.90 20.00 20.10 23.90 24.00 24.10 e 0.50 bsc 0.50 bsc l 0.45 0.60 0.75 0.45 0.60 0.75 ccc 0.10 0.10 theta 0 7 deg 0 7 deg notes: 1. all dimensions are in millimeters. 2. bsc ? basic spacing between centers.
54sx family fpgas 61 thin quad flat packs (vqfp) jedec equiv vqfp 100 mo-136 dimension min nom max a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b0.17 0.27 c 0.09 0.20 d/e 15.75 16.00 16.25 d1/e1 13.90 14.00 14.10 e0.50 bsc l 0.45 0.60 0.75 ccc 0.10 theta 0 7 deg notes: 1. all dimensions are in millimeters. 2. bsc ? basic spacing between centers.
62 package mechanical drawings (continued) 144-pin fbga e 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m e1 d1 detail a a2 // ccc c // bbb c c a1 ? b a aaa c c d1/e1 sq detail a side view d/d2 e/e2 top view bottom view pin one corner
54sx family fpgas 63 fine pitch ball grid array (fbga) fbga 144 dimension min. nom. max. a 1.35 1.45 1.55 a1 0.35 0.40 0.45 a2 0.65 0.70 0.75 aaa 0.15 b 0.45 0.50 0.55 bbb 0.20 c0.35 ccc 0.25 d 12.80 13.00 13.20 d1 11.00 bsc d2 12.80 13.00 13.20 e 12.80 13.00 13.20 e1 11.00 bsc e2 12.80 13.00 13.20 e 0.9 1.00 1.10 notes: 1. all dimensions are in millimeters. 2. bsc ? basic spacing between centers.
64 package mechanical drawings (continued) plastic ball grid array (pbga313) r0.025 typ. detail a 30 a2 // ccc c // bbb c c a1 ? b a aaa c c e2 e d2 d top view d1/e1 sq detail a side view bottom view r (dia.) pin one corner pin one corner e 1 3 5 7 9 11 13 15 19 21 23 25 17 2 4 6 8 10 12 14 18 20 22 24 16 e1 d1 c e g j l n r u w aa ac d f h k m p t v y ab ad b ae a
65 54sx family fpgas package mechanical drawings (continued) plastic ball grid array (pbga329) r0.025 typ. detail a 30 a2 // ccc c // bbb c c a1 ? b a aaa c c e2 e d2 d top view d1/e1 sq detail a side view bottom view pin one corner pin one corner e 1 3 5 7 9 11 13 15 19 21 23 17 2 4 6 8 10 12 14 18 20 22 16 e1 d1 c e g j l n r u w aa ac d f h k m p t v y ab b a
66 plastic ball grid array (pbga) jedec equivalent pbga313 pbga329 dimension min. nom. max. min. nom. max. a 2.12 2.33 2.52 2.17 2.33 2.70 a1 0.50 0.60 0.70 0.50 0.60 0.70 a2 1.12 1.17 1.22 1.10 1.20 1.30 d 34.80 35.00 35.20 30.80 31.00 31.20 d1 30.48 bsc 27.94 bsc d2 29.50 30.00 30.70 27.90 28.00 28.10 e 34.80 35.00 35.20 30.80 31.00 31.20 e1 30.48 bsc 27.94 bsc e2 29.50 30.00 30.70 27.90 28.00 28.10 b 0.60 0.76 0.90 0.60 0.76 0.90 c 0.53 0.56 0.61 0.53 0.60 0.70 aaa 0.15 0.20 bbb n/a 0.20 ccc 0.35 0.25 e 1.27 typ. 1.27 typ. notes: 1. all dimensions are in millimeters. 2. bsc ? basic spacing between centers.
67 54sx family fpgas
68
69 54sx family fpgas
actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. http://www.actel.com actel europe ltd. daneshill house, lutyens close basingstoke, hampshire rg24 8ag united kingdom tel: +44-(0)125-630-5600 fax: +44-(0)125-635-5420 actel corporation 955 east arques avenue sunnyvale, california 94086 usa tel: (408) 739-1010 fax: (408) 739-1540 actel asia-pacific exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan tel: +81-(0)3-3445-7671 fax: +81-(0)3-3445-7668 517 2 1 3 7 - 3/5. 0 0

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